1. Field of the Invention
The invention relates to a field effect transistor provided with a vertically oriented semiconductor column of a diameter in the nanometer range (nano-wire) disposed between a source electrode and a drain electrode and annularly surrounded at an insulating space by a gate electrode as well as to a method of its fabrication.
2. The Prior Art
Thin layer transistors are known in which semiconductor material is deposited in a planar arrangement on flexible substrates. However, mechanical stresses on the substrates easily lead to a release of the semiconductors from the substrate or to other damages and, hence, to functional failure.
It has already been proposed to fabricate transistors of the nanometer range by the formation of ion trace channels by ion bombardment in a foil composite consisting of two plastic foils and an intermediate layer of metal and by sensitizing the ion trace channels for subsequent etching. Semiconductor material is injected into the etched micro-holes by electro deposition or chemical bath precipitation. Source electrodes and drain electrodes are formed by subsequently metalizing the upper and lower surface of the foil compound. The center layer of metal serves as the gate electrode.
The advantage of the cylindrical and vertical arrangement of these transistors is the mechanical robustness since the foil is flexible and extensible. Moreover, the organic foil material is substantially softer than the inorganic semiconductor material. As a result, occurring bending, shear and compressive forces are almost completely absorbed by the foil material so that under bending, flexing and tensile forces the characteristic curve of the transistor and other electrical parameters remain substantially constant.
Since micro-holes can be fabricated down to 30 nm and filled with semiconductor material, transistors on the nanometer scale can be fabricated without lithography and without any masking technique.
Depending upon the type of precipitation of the semiconductor material, the process leads to polycrystalline semiconductor columns. The ration of length to diameter of the semiconductor columns is also limited by the required crystal growth within the micro-holes. Overall, the method of fabricating the transistors is still too complex since hitherto the ion bombardment can be carried out only in select scientific environments.